HT46R47E/HT46C47E
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
tion cycle has 64 PWM input clock period. In a (6+2) bit
PWM function, the contents of the PWM register is di-
vided into two groups. Group 1 of the PWM register is
denoted by DC which is the value of PWM.7~PWM.2.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0. If the PWM function is en-
abled, the PWM signal will appear on PD0 (if PD0 is op-
erating in output mode). Writing ²1² to PD0 data register
will enable the PWM output function and writing ²0² will
force the PD0 to remain at ²0². The I/O functions of PD0
are as shown.
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a PWM cycle, the duty cycle of each modulation cycle
is shown in the table.
Parameter
AC (0~3)
Duty Cycle
DC+1
64
I/O
I/P
O/P
I/P
O/P
i<AC
Modulation cycle i
(i=0~3)
Mode (Normal) (Normal) (PWM)
(PWM)
DC
64
Logical
Input
Logical
Output
Logical
Input
i³AC
PD0
PWM
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
PWM
PWM
PWM Cycle
Frequency
PWM Cycle
Duty
Modulation
Frequency
The microcontroller provides 1 channel (6+2) bits PWM
output shared with PD0. The PWM channel has its data
register denoted as PWM (1AH). The frequency source
of the PWM counter comes from fSYS. The PWM register
is an eight bits register. The waveforms of PWM output
are as shown. Once the PD0 is selected as the PWM
output and the output function of PD0 is enabled
(PDC.0=²0²), writing 1 to PD0 data register will enable
the PWM output function and writing ²0² will force the
PD0 to stay at ²0².
f
SYS/64
fSYS/256
[PWM]/256
A/D Converter
The 4 channels and 9-bit resolution A/D converter are
implemented in this microcontroller. The reference volt-
age is VDD. The A/D converter contains 4 special regis-
ters which are; ADRL (20H), ADRH (21H), ADCR (22H)
and ACSR (23H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
A PWM cycle is divided into four modulation cycles
(modulation cycle 0~modulation cycle 3). Each modula-
S
Y
S
[
P
W
M
]
=
1
0
0
P
P
P
P
W
W
W
W
M
M
M
M
2
5
/
6
4
2
2
2
2
5
5
6
6
/
/
/
/
6
6
6
6
4
4
4
4
2
5
/
6
4
2
5
/
6
4
2
2
2
2
5
6
6
6
/
/
/
/
6
6
6
6
4
4
4
4
[
[
[
P
P
P
W
W
W
M
M
M
]
]
]
=
=
=
1
1
1
0
0
0
1
2
3
2
2
2
6
6
6
/
/
/
6
6
6
4
4
4
2
5
/
6
4
2
5
/
6
4
2
5
/
6
4
2
5
/
6
4
2
6
/
6
4
2
5
/
6
4
P
W
M
m
o
d
u
l
a
t
i
o
n
p
e
r
i
o
d
:
6
4
/
f
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
1
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
2
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
3
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
P
W
M
c
y
c
l
e
:
2
5
6
/
f
PWM
Rev. 1.30
17
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
