HT46R47E/HT46C47E
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that, in this operat-
ing mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared au-
tomatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ETI can disable the interrupt
service.
In the case of timer/event counter OFF condition, writ-
ing data to the timer/event counter preload register will
also reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow oc-
curs. When the timer/event counter (reading TMR) is read,
the clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into con-
sideration by the programmer.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal.
Bit No.
Label
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
0
1
2
PSC0
PSC1
PSC2
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
3
TE
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable or disable timer counting
(0=disabled; 1=enabled)
4
5
TON
¾
Unused bits, read as ²0²
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
TM0
TM1
TMRC (0EH) Register
P
W
M
(
6
+
2
)
C
o
m
p
a
r
e
T
o
P
D
0
C
i
r
c
u
i
t
f
S Y S
8
-
s
t
a
g
e
P
r
e
s
c
a
l
e
r
f
I N T
D
a
t
a
B
u
s
8
-
1
M
U
X
T
M
1
8
-
B
i
t
T
i
m
e
r
/
E
v
e
n
t
R
e
l
o
a
d
T
M
0
C
o
u
n
t
e
r
P
r
e
l
o
a
d
P
S
C
2
~
P
S
C
0
T
M
R
R
e
g
i
s
t
e
r
T
E
8
-
B
i
t
T
i
m
e
r
/
E
v
e
n
t
P
u
l
s
e
W
i
n
d
t
h
O
v
e
r
f
l
o
w
T
T
T
M
M
O
1
C
o
u
n
t
e
r
M
e
a
s
u
r
e
m
e
n
t
t
o
I
n
t
e
r
r
u
p
t
0
M
o
d
e
C
o
t
r
o
l
N
1
/
2
P
F
D
Timer/Event Counter
Rev. 1.30
15
July 13, 2005