HT46R47E/HT46C47E
The ALU not only saves the results of a data operation but
also changes the status register.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in-
terrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC may be set to
allow interrupt nesting. If the stack is full, the interrupt re-
quest will not be acknowledged, even if the related inter-
rupt is enabled, until the SP is decremented. If immediate
service is desired, the stack must be prevented from be-
coming full.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag can be affected only by exe-
cuting the ²HALT² or ²CLR WDT² instruction or a
system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stack is not full and the external interrupt is active, a sub-
routine call to location 04H will occur. The interrupt re-
quest flag (EIF) and EMI bits will be cleared to disable
other interrupts.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF;bit 5 of INTC), caused by a timer overflow. When the
interrupt is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur. The re-
lated interrupt request flag (TF) will be reset and the EMI
bit cleared to disable further interrupts.
Interrupt
The device provides an external interrupt, internal
timer/event counter interrupt and A/D converter inter-
rupts. The Interrupt Control Register (INTC;0BH) con-
tains the interrupt control bits to set the enable or disable
and the interrupt request flags.
Bit No.
Label
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
4
PDF
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
5
TO
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.30
10
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
