HT46R47E/HT46C47E
The registers¢ states are summarized in the following table.
Reset
WDT Time-out
RES Reset
RES Reset
(HALT)
WDT Times-out
(HALT)*
Register
TMR
(Power On)
(Normal Operation) (Normal Operation)
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1000
xxxx xxxx
00-0 1000
uuuu uuuu
uu-u uuuu
TMRC
Program
Counter
000H
000H
000H
000H
000H
MP
-xxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
--00 xxxx
-000 0000
1111 1111
1111 1111
---- 1111
---- 1111
---- ---1
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--1u uuuu
-000 0000
1111 1111
1111 1111
---- 1111
---- 1111
---- ---1
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
-000 0000
1111 1111
1111 1111
---- 1111
---- 1111
---- ---1
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--01 uuuu
-000 0000
1111 1111
1111 1111
---- 1111
---- 1111
---- ---1
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
---- uuuu
---- ---u
ACC
TBLP
TBLH
STATUS
INTC
PA
PAC
PB
PBC
PD
PDC
PWM
ADRL
ADRH
ADCR
ACSR
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
xxxx xxxx
x--- ----
xxxx xxxx
x--- ----
xxxx xxxx
x--- ----
xxxx xxxx
x--- ----
uuuu uuuu
u--- ----
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
uuuu uuuu
uuuu uuuu
u--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Timer/Event Counter
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter and the clock may
come from an external source or the system clock.
Using external clock input allows the user to count exter-
nal events, measure time internals or pulse widths, or
generate an accurate time base. While using the inter-
nal clock allows the user to generate an accurate time
base.
counting is based on the fINT
.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current con-
tents in the timer/event counter to FFH. Once overflow oc-
curs, the counter is reloaded from the timer/event counter
preload register and generates the interrupt request flag
(TF; bit 5 of INTC) at the same time.
The timer/event counter can generate PFD signal by us-
ing external or internal clock and PFD frequency is de-
termine by the equation fINT/[2´(256-N)].
There are 2 registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer/event counter preload
register and reading TMR retrieves the contents of the
timer/event counter. The TMRC is a timer/event counter
control register, which defines some options.
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR has received a
transient from low to high (or high to low if the TE bits is
²0²) it will start counting until the TMR returns to the orig-
inal level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
Rev. 1.30
14
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
