HT46R47E/HT46C47E
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
Controls the master (global) interrupt (1=enabled; 0=disabled)
Controls the external interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
Controls the A/D converter interrupt (1=enabled; 0=disabled)
External interrupt request flag (1=active; 0=inactive)
ETI
EADI
EIF
TF
Internal Timer/Event Counter request flag (1=active; 0=inactive)
A/D converter request flag (1=active; 0=inactive)
ADF
For test mode used only.
7
¾
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC (0BH) Register
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC), caused
by an end of A/D conversion. When the interrupt is en-
abled, the stack is not full and the ADF is set, a subrou-
tine call to location 0CH will occur. The related interrupt
request flag (ADF) will be reset and the EMI bit cleared
to disable further interrupts.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
D
D
4
7
0
p
F
O
S
C
1
O
S
C
1
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
f
S
Y
S
/
4
O
S
C
2
O
S
C
2
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
R
C
O
s
c
i
l
l
a
t
o
r
System Oscillator
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se-
lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
Interrupt Source
External Interrupt
Priority
Vector
04H
1
2
3
Timer/Event Counter Overflow
A/D Converter Interrupt
08H
0CH
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), A/D converter request
flag (ADF), enable timer/event counter bit (ETI), enable
external interrupt bit (EEI), enable A/D converter inter-
rupt bit (EADI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC) which is
located at 0BH in the data memory. EMI, EEI, ETI, EADI
are used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF, EIF, ADF)
are set, they will remain in the INTC register until the in-
terrupts are serviced or cleared by a software instruc-
tion.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2 with pull-high resistor, which
can be used to synchronize external logic. The RC os-
cillator provides the most cost effective solution. How-
ever, the frequency of oscillation may vary with VDD,
temperatures and the chip itself due to process varia-
tions. It is, therefore, not suitable for timing sensitive
operations where an accurate oscillator frequency is
desired.
Rev. 1.30
11
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
