HT46R47E/HT46C47E
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a
²CALL²
is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 6 return ad-
dresses are stored).
Data Memory
-
RAM
The data memory is designed with 85´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(64´8). Most are read/write, but some are read only.
The special function registers include the indirect ad-
dressing register (00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer register (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
PWM data register (PWM;1AH), the A/D result
lower-order byte register (ADRL;20H), the A/D result
higher-order byte register (ADRH;21H), the A/D control
register (ADCR;22H), the A/D clock setting register
(ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 40H is re-
served for future expanded usage and reading these lo-
cations will get
²00H².
The general purpose data
memory, addressed from 40H to 7FH, is used for data
and control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by
²SET
[m].i² and
²CLR
[m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result
²1².
Any writing operation to MP will only transfer the
lower 7-bit data to MP.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
3 F H
4 0 H
A D R L
A D R H
A D C R
A C S R
P D
P D C
P W M
P A
P A C
P B
P B C
S p e c ia l P u r p o s e
D A T A M E M O R Y
T M R
T M R C
S T A T U S
IN T C
A C C
P C L
T B L P
T B L H
In d ir e c t A d d r e s s in g R e g is te r
M P
G e n e ra l P u rp o s e
D A T A M E M O R Y
(6 4 B y te s )
: U n u s e d
R e a d a s "0 0 "
7 F H
RAM Mapping
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit
-
ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ ....)
Rev. 1.30
9
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
