HT46R23/HT46C23
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initial-
ization is not required.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL D1 D0
¾
¾
¾
¾
¾
¾
Important Note for A/D initialization:
ADRH D9 D8 D7 D6 D5 D4 D3 D2
Special care must be taken to initialize the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialization is implemented
Note: D0~D9 is A/D conversion result data bit
LSB~MSB.
ADRL (24H), ADRH (25H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
mov
mov
mov
a,00000001B
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
a,00100000B
ADCR,a
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
set
clr
START
START
START
; reset A/D
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
jmp
mov
mov
mov
mov
polling_EOC
a,ADRH
adrh_buffer,a
a,ADRL
; read conversion result high byte value from the ADRH register
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
adrl_buffer,a
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
mov
a,00000001B
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
ADCR,a
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Rev. 2.11
19
December 29, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
