HT46R23/HT46C23
Bit No.
Label
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
0
1
2
PSC0
PSC1
PSC2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
3
TE
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable or disable timer counting
(0=disabled; 1=enabled)
4
5
TON
¾
Unused bits, read as ²0²
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
TM0
TM1
TMRC (0EH) Register
Input/Output Ports
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 3-bit of port C and 6-bit of port D are
not physically implemented; on reading them a ²0² is re-
turned whereas writing then results in a no-operation.
See Application note.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under soft-
ware control. To function as an input, the corresponding
latch of the control register must write ²1². The input
source also depends on the control register. If the con-
trol register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode always remain-
ing its original functions. Once the PFD option is se-
lected, the PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Rev. 2.11
15
December 29, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
