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HT46R12(24SOP-A) 参数 Datasheet PDF下载

HT46R12(24SOP-A)图片预览
型号: HT46R12(24SOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO24]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 45 页 / 314 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R12  
·
PPG0C control register  
Bit No.  
7
6
5
4
3
2
1
0
PPG0C (20H)  
POR value  
P0ST  
0
P0RSEN P0SPEN P0PSC2 P0PSC1 P0PSC0 CMP1EN CMP0EN  
0
0
0
0
0
0
0
CMP0EN: Enables or disables the Comparator 0 (0=disable, 1=enable)  
CMP1EN: Enables or disables the Comparator 1 (0=disable, 1=enable)  
P0PSC0, P0PSC1, P0PSC2: These three bits select the PPG0 timer prescaler rate.  
P0SPEN: Enables or disables the stopping of the PPG0 timer using C0VO trigger input (0=disable, 1=enable)  
P0RSEN: Enables or disables the restarting of the PPG0 timer using C1VO trigger input. (0=disable, 1=enable)  
P0ST: PPG0 software trigger bit. (0=Stop PPG0, 1=Restart PPG0)  
The CMP0EN and CMP1EN bits are used as the comparators enable or disable bits, if the CMP0EN is cleared to ²0²,  
the Comparator 0 is disabled, the PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins, if the CMP0EN is set to  
²1², the Comparator 0 is enabled, PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT can still be used as input pins. If the  
CMP1EN is cleared to ²0², the Comparator 1 is disabled, the PC3/C1OUT is a GPIO pin, If the CMP1EN is set to ²1²,  
the Comparator 1 is enabled, PC3 can still be used as input pin.  
PPG0C: CMP0EN, CMP1EN comparators enable/disable bits  
CMP0EN  
Description  
Disable the Comparator 0. PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins.  
Enable the Comparator 0  
0
1
CMP1EN  
Description  
Disable the Comparator 1. PC3/C1OUT is a PGIO pin.  
Enable the Comparator 1  
0
1
The bits 4~2 of the PPG0 control register (PPG0C) can be used to define the pre-scaling stages of the PPG0 timer  
counter clock.  
PPG0C: PPG0 timer prescaler rate bits  
P0PSC2  
P0PSC1  
P0PSC0  
Define the prescaler stages  
P0fS=fSYS  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P0fS=fSYS/2  
P0fS=fSYS/4  
P0fS=fSYS/8  
P0fS=fSYS/16  
P0fS=fSYS/32  
P0fS=fSYS/64  
P0fS=fSYS/128  
Rev. 1.20  
18  
February 24, 2006  
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