HT46RU25/HT46CU25
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1² when the
START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified,
otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START
bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note
that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required.
Bit No. Label
Function
Selects the A/D converter clock source
00= system clock/2
0
1
ADCS0
ADCS1
01= system clock/8
10= system clock/32
11= undefined
2~6
7
¾
Unused bit, read as ²0²
TEST For test mode use only
ACSR (27H) Register
Bit No. Label
Function
0
1
2
ACS0
ACS1 Defines the analog channel select
ACS2
3
4
5
PCR0
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption.
PCR1
PCR2
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, other-
wise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
6
7
EOCB
START
Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PB7
PB7
PB7
PB7
PB7
PB7
PB7
AN7
PB6
PB6
PB6
PB6
PB6
PB6
PB6
AN6
PB5
PB5
PB5
PB5
PB5
PB5
AN5
AN5
PB4
PB4
PB4
PB4
PB4
AN4
AN4
AN4
PB3
PB3
PB3
PB3
AN3
AN3
AN3
AN3
PB2
PB2
PB2
AN2
AN2
AN2
AN2
AN2
PB1
PB1
AN1
AN1
AN1
AN1
AN1
AN1
PB0
AN0
AN0
AN0
AN0
AN0
AN0
AN0
Port B Configuration
Rev. 1.30
25
March 9, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
