HT46RU25/HT46CU25
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, this will be executed im-
mediately after the dummy period is finished.
RT2
0
RT1
0
RT0
0
RTC Clock Divided Factor
8
2 *
9
0
0
1
2 *
10
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
0
1
0
2
2
*
*
11
0
1
1
12
13
14
15
Reset
1
0
0
2
There are three ways in which a reset may occur:
1
0
1
2
2
2
·
·
·
RES reset during normal operation
RES reset during HALT
1
1
0
1
1
1
WDT time-out reset during normal operation
Note: ²*² not recommended to be used
Power Down Operation - HALT
The WDT time-out during HALT differs from other chip re-
set conditions, for it can perform a ²warm reset² that re-
sets only the program counter and SP, leaving the other
circuits in their original state. Some registers remain un-
affected during other reset conditions. Most registers are
reset to the ²initial condition² when the reset conditions
are met. Examining the PDF and TO flags, the program
can distinguish between different ²chip resets².
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
·
The system oscillator is turned off but the WDT oscil-
lator keeps running (if the WDT oscillator or the real
time clock is selected).
·
·
The contents of the on-chip RAM and registers remain
unchanged.
V
D
D
The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the
real time clock).
m
0 . 0 1 F *
1
0
0
k
·
·
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
R
E
S
1
0
k
The system quits the HALT mode by way of an external
reset, an interrupt, an external falling edge signal on port
A or a WDT overflow. An external reset causes a device
initialization and the WDT overflow performs a ²warm
reset². After examining the TO and PDF flags, the cause
for a chip reset can be determined. The PDF flag is
cleared by system power-up or by executing the ²CLR
WDT² instruction and is set when executing the ²HALT²
instruction. On the other hand, the TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, and
leaves the other circuits in their original status.
m
0 . 1 F *
Reset Circuit
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
W
D
T
T
i
m
e
-
o
u
t
R
e
s
e
t
E
x
t
e
r
n
a
l
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by option. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequences may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. But if the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. When an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. If a
wake-up event occurs, it takes 1024 fSYS (system clock
period) to resume normal operation. In other words, a
dummy period is inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
R
E
S
C
o
l
d
R
e
s
e
t
S
S
T
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
u
n
t
e
r
P
o
w
e
r
-
o
n
D
e
t
e
c
t
i
o
n
Reset Configuration
V
D
D
R
E
S
t
S S T
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
Reset Timing Chart
Rev. 1.30
15
March 9, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
