HT46R63/HT46C63
All these kinds of interrupts have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified location(s) in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register are altered by the interrupt service program,
which corrupts the desired control sequence, the pro-
grammer should save these contents first.
Interrupts, occurring in the interval between rising edge
of two consecutive T2 pulses, will be serviced on the
later of the two T2 pulses, if the corresponding interrupts
are enabled. In the case of simultaneous requests the
priorities in the follow table apply. These can be masked
by clearing the EMI bit.
Interrupt Source
External Interrupt 0
Priority Vector
1
2
004H
008H
External Interrupt 1
External interrupts are triggered by a high to low and/or
low to high transition of INT0/INT1 and the related inter-
rupt request flag (bit 4/5 of INTC0 ) will be set. When the
interrupt is enabled, the stack is not full and the external
interrupt is active, a subroutine call to location
004H/008H will occur. The external interrupt request
flag and EMI bits will cleared to disable other interrupts.
Timer/Event Counter Overflow
Interrupt
3
00CH
Time Base Time-out Interrupt
End of A/D Conversion Interrupt
RTC Time-out Interrupt
4
5
6
010H
014H
018H
The external interrupt 0/1 request flags (EI0F/EI1F),
timer/event counter interrupt request flag (TF), time
base interrupt request flag (TBF), A/D converter inter-
rupt request flag (ADF), RTC interrupt request flag
(RTF), enable external interrupt 0/1 (EE0I/EE1I), enable
timer/event counter interrupt bit (ETI), enable time base
interrupt (ETBI), enable A/D converter interrupt (EADI),
enable RTC interrupt (ERTI) and enable master inter-
rupt bit(EMI) constitute interrupt control registers
(INTC0/INTC1) which is located at 0BH/1EH in the data
memory. EMI, EE0I, EE1I, ETI, EADI and ERTI are used
to control the enabling/disabling of interrupts. These bits
prevent the requested interrupts from being serviced.
Once the interrupt request flags (EI0F, EI1F, TF, TBF,
ADF, RTF) are set, they will remain in the INTC0/INTC1
until the interrupts are serviced or cleared by software
instructions.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag (bit
6 of INTC0), caused by a timer overflow. When the inter-
rupt is enabled, the stack is not full and the timer/event
counter interrupt request flag is set, a subroutine call to
location 00CH will occur. The related interrupt request
flag will be reset and the EMI bit cleared to disable fur-
ther interrupts.
The time base time-out interrupt is initialized by setting
the time base time-out interrupt request flag (bit 4 of
INTC1), caused by a time base time-out. When the in-
terrupt is enabled, the stack is not full and the time base
time-out interrupt request flag is set, a subroutine call to
location 010H will occur. The related interrupt request
flag will be reset and the EMI bit cleared to disable fur-
ther interrupts.
The A/D converter end-of-conversion interrupt is initial-
ized by setting the A/D end-of-conversion interrupt re-
quest flag (bit 5 of INTC1), caused by an end of A/D
conversion. When the interrupt is enabled, the stack is
not full and the end of A/D conversion interrupt request
flag is set, a subroutine call to location 014H will occur.
The related interrupt request flag will be reset and the
EMI bit cleared to disable further interrupts.
It is suggested that a program does not use the ²call²
within a interrupt subroutine. It because interrupts often
occur in an unpredictable manner or need to be serviced
immediately in some applications. If only one stack is
left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine. The defini-
tions of INTC0 and INTC1 registers are as shown.
The real time clock time-out interrupt is initialized by set-
ting the real time clock interrupt request flag (bit 6 of
INTC1), caused by a RTC time-out. When the interrupt
is enabled, the stack is not full and the RTC time-out in-
terrupt request flag is set, a subroutine call to location
018H will occur. The related interrupt request flag will be
reset and the EMI bit cleared to disable further inter-
rupts.
Bit No. Label
Function
INTC0 Register
Controls the master (global) interrupt
(1= enabled; 0= disabled)
0
1
2
3
4
EMI
EEI0
EEI1
ETI
Controls the external interrupt 0
(1= enabled; 0= disabled)
Controls the external interrupt 1
(1= enabled; 0= disabled)
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to ²1² (of course, if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
Controls the timer/event counter over-
flow interrupt (1= enabled; 0= disabled)
External interrupt 0 request flag
(1= active; 0= inactive)
EIF0
Rev. 1.90
12
May 17, 2004
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