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HT45R37-A(28SSOP-A) 参数 Datasheet PDF下载

HT45R37-A(28SSOP-A)图片预览
型号: HT45R37-A(28SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 12MHz, CMOS, PDSO28]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 100 页 / 666 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT45R37  
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Pulse Width Measure Mode Timing Chart  
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PFD Output Control  
Timer/Event Counter will stop counting. If the Active  
Edge Select bit is high, the Timer/Event Counter will be-  
gin counting once a low to high transition has been re-  
ceived on the external timer pin and stop counting when  
the external timer pin returns to its original low level. As  
before, the enable bit will be automatically reset to zero  
and the Timer/Event Counter will stop counting. It is im-  
portant to note that in the Pulse Width Measurement  
Mode, the enable bit is automatically reset to zero when  
the external control signal on the external timer pin re-  
turns to its original level, whereas in the other two  
modes the enable bit can only be reset to zero under  
program control.  
As the external timer pin is shared with an I/O pin, to en-  
sure that the pin is configured to operate as a pulse  
width measurement pin, two things have to happen. The  
first is to ensure that the Operating Mode Select bits in  
the Timer Control Register place the Timer/Event Coun-  
ter in the Pulse Width Measurement Mode, the second  
is to ensure that the port control register configures the  
pin as an input.  
Programmable Frequency Divider - PFD  
The Programmable Frequency Divider provides a  
means of producing a variable frequency output suitable  
for applications requiring a precise frequency generator.  
The residual value in the Timer/Event Counter, which  
can now be read by the program, therefore represents  
the length of the pulse received on the external timer  
pin. As the enable bit has now been reset, any further  
transitions on the external timer pin will be ignored. Not  
until the enable bit is again set high by the program can  
the timer begin further pulse width measurements. In  
this way, single shot pulse measurements can be easily  
Made.  
The PFD output is pin-shared with the I/O pin PA3. The  
PFD function is selected via configuration option, how-  
ever, if not selected, the pin can operate as a normal I/O  
pin.  
The clock source for the PFD circuit can originate from  
either Timer/Event Counter 0 or Timer/Event Counter 1  
overflow signal selected via configuration option. The  
output frequency is controlled by loading the required  
values into the timer registers and prescaler registers to  
give the required division ratio. The timer will begin to  
count-up from this preload register value until full, at  
which point an overflow signal is generated, causing the  
PFD output to change state. The timer will then be auto-  
matically reloaded with the preload register value and  
continue counting-up.  
It should be noted that in this mode the Timer/Event  
Counter is controlled by logical transitions on the exter-  
nal timer pin and not by the logic level. When the  
Timer/Event Counter is full and overflows, an interrupt  
signal is generated and the Timer/Event Counter will re-  
load the value already loaded into the preload register  
and continue counting. The interrupt can be disabled by  
ensuring that the Timer/Event Counter Interrupt Enable  
bit in the corresponding Interrupt Control Register, is re-  
set to zero.  
Rev. 1.20  
24  
February 25, 2011  
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