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HT45R37-A(28SSOP-A) 参数 Datasheet PDF下载

HT45R37-A(28SSOP-A)图片预览
型号: HT45R37-A(28SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 12MHz, CMOS, PDSO28]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 100 页 / 666 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT45R37  
a prescaler, the value of which is determined by the  
Prescaler Rate Select bits TnPSC2~TnPSC0, which are  
bits 2~0 in the Timer Control Register. After the other  
bits in the Timer Control Register have been setup, the  
enable bit TnON or TnON, which is bit 4 of the Timer  
Control Register, can be set high to enable the  
Timer/Event Counter to run. Each time an internal clock  
cycle occurs, the Timer/Event Counter increments by  
one. When it is full and overflows, an interrupt signal is  
generated and the Timer/Event Counter will reload the  
value already loaded into the preload register and con-  
tinue counting. The interrupt can be disabled by ensur-  
ing that the Timer/Event Counter Interrupt Enable bit in  
the corresponding Interrupt Control Register, is reset to  
zero.  
corresponding Interrupt Control Register, is reset to  
zero.  
As the external timer pin is shared with an I/O pin, to en-  
sure that the pin is configured to operate as an event  
counter input pin, two things have to happen. The first is  
to ensure that the Operating Mode Select bits in the  
Timer Control Register place the Timer/Event Counter in  
the Event Counting Mode, the second is to ensure that  
the port control register configures the pin as an input. It  
should be noted that in the event counting mode, even if  
the microcontroller is in the Power Down Mode, the  
Timer/Event Counter will continue to record externally  
changing logic events on the timer input pin. As a result  
when the timer overflows it will generate a timer interrupt  
and corresponding wake-up source.  
Configuring the Event Counter Mode  
Configuring the Pulse Width Measurement Mode  
In this mode, a number of externally changing logic  
events, occurring on the external timer pin, can be re-  
corded by the Timer/Event Counter. To operate in this  
mode, the Operating Mode Select bit pair, TnM1/TnM0,  
in the Timer Control Register must be set to the correct  
value as shown.  
In this mode, the Timer/Event Counter can be utilised to  
measure the width of external pulses applied to the ex-  
ternal timer pin. To operate in this mode, the Operating  
Mode Select bit pair, TnM1/TnM0, in the Timer Control  
Register must be set to the correct value as shown.  
Control Register Operating Mode  
Bit7 Bit6  
Bit7 Bit6  
Control Register Operating Mode  
Select Bits for the Pulse Width  
1
1
Select Bits for the Event Counter Mode  
Measurement Mode  
0
1
In this mode the internal clock, fSYS, is used as the inter-  
nal clock for the Timer/Event Counter. However, the  
clock source, fSYS, for the 8-bit timer is further divided by  
a prescaler, the value of which is determined by the  
Prescaler Rate Select bits TnPSC2~TnPSC0, which are  
bits 2~0 in the Timer Control Register. After the other  
bits in the Timer Control Register have been setup, the  
enable bit TnON, which is bit 4 of the Timer Control Reg-  
ister, can be set high to enable the Timer/Event Counter,  
however it will not actually start counting until an active  
edge is received on the external timer pin.  
In this mode, the external timer pin, is used as the  
Timer/Event Counter clock source, however it is not di-  
vided by the internal prescaler. After the other bits in the  
Timer Control Register have been setup, the enable bit  
TnON, which is bit 4 of the Timer Control Register, can  
be set high to enable the Timer/Event Counter to run. If  
the Active Edge Select bit, TnE, which is bit 3 of the  
Timer Control Register, is low, the Timer/Event Counter  
will increment each time the external timer pin receives  
a low to high transition. If the Active Edge Select bit is  
high, the counter will increment each time the external  
timer pin receives a high to low transition. When it is full  
and overflows, an interrupt signal is generated and the  
Timer/Event Counter will reload the value already  
loaded into the preload register and continue counting.  
The interrupt can be disabled by ensuring that the  
Timer/Event Counter Interrupt Enable bit in the  
If the Active Edge Select bit TnE, which is bit 3 of the  
Timer Control Register, is low, once a high to low transi-  
tion has been received on the external timer pin, the  
Timer/Event Counter will start counting until the external  
timer pin returns to its original high level. At this point the  
enable bit will be automatically reset to zero and the  
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Timer Mode Timing Chart  
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Event Counter Mode Timing Chart  
Rev. 1.20  
23  
February 25, 2011  
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