HT16C21
Display RAM Read Operation
In this mode, the master reads the HT16C21 data after setting the slave address. Following the R/W bit (=’0”)
●
is an acknowledge bit, a command byte and the register address byte which is written to the internal address
pointer. After the start address of the Read Operation has been configured, another START condition and the
slave address transferred on the I2C interface followed by the R/W bit (=’1”). Then the MSB of the data which
was addressed is transmitted first on the I2C interface. The address pointer is only incremented by 1 after the
reception of an acknowledge clock. That means that if the device is configured to transmit the data at the
address of AN+1, the master will read and acknowledge the transferred new data byte and the address pointer is
incremented to AN+2. After the internal address pointer reaches the maximum memory address, which is 09H
for 1/4 duty drive mode or 0FH for 1/8 duty drive mode, the address pointer will be reset to 00H.
This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
●
Slave Address
Command byte
Register Address byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
S
0
1
1
1
0
0
0
0
P
1st
2nd
Write
ACK
ACK
ACK
Device Address
Data byte
D4 D3
Data byte
D4 D3
Data byte
D7
D6
D5
D2
D1
D0
D7
D6
D5
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
S
0
1
1
1
0
0
0
1
P
NACK
1st data
2nd data
Nth data
Read
ACK
ACK
ACK
ACK
Rev. 1.00
18
November 22, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
