HT16C21
Acknowledge
Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed on the
I2C interface by the receiver. The master generates an extra acknowledge related clock pulse.
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A slave receiver which is addressed must generate an acknowledge, ACK, after the reception of each byte.
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The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it
remains stable low during the high period of this clock pulse.
A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the
last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high
during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
●
Data Output
by Transmitter
not acknowledge
Data Outptu
by Receiver
acknowledge
SCL From
Master
1
2
7
8
9
S
START
condition
clock pulse for
acknowledgement
Slave Addressing
The slave address byte is the first byte received following the START condition form the master device. The
first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be
performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation.
●
The HT16C21 address bits are “0111000”. When an address byte is sent, the device compares the first seven
●
bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line.
Slave Address
MSB
LSB
R/W
0
1
1
1
0
0
0
Rev. 1.00
16
November 22, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
