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HD6473434F16 参数 Datasheet PDF下载

HD6473434F16图片预览
型号: HD6473434F16
PDF下载: 下载PDF文件 查看货源
内容描述: 12伏不能应用于S -掩模模型(单电源规格) ,因为这可能会永久损坏设备。 [12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.]
分类和应用: 外围集成电路微控制器可编程只读存储器时钟
文件页数/大小: 752 页 / 2557 K
品牌: HITACHI [ HITACHI SEMICONDUCTOR ]
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Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The  
I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at  
nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL  
to 1 to indicate that the bus has been taken by another master. At the same time, it sets the IRIC bit  
in ICSR to generate an interrupt request.  
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is  
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive  
mode.  
Bit 3: AL  
Description  
0
Bus arbitration won  
(Initial value)  
This bit is cleared to 0 at the following times:  
When ICDR data is written (transmit mode) or read (receive mode)  
When AL is read while AL = 1, then 0 is written in AL  
1
Arbitration lost  
This bit is set to 1 at the following times:  
If the internal SDA signal and bus line disagree at the rise of SCL in master  
transmit mode  
If the internal SCL is high at the fall of SCL in master transmit mode  
Bit 2—Slave Address Recognition Flag (AAS): When the addressing format is selected (FS = 0)  
in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits  
SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.  
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS  
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive  
mode.  
Bit 2: AAS  
Description  
0
Slave address or general call address not recognized  
This bit is cleared to 0 at the following times:  
(Initial value)  
When ICDR data is written (transmit mode) or read (receive mode)  
When AAS is read while AAS = 1, then 0 is written in AAS  
1
Slave address or general call address recognized  
This bit is set to 1 at the following times:  
When the slave address or general call address is detected in slave receive  
mode  
294  
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