The SAR register can be accessed when ICE is 0. The ICMR register can be accessed when ICE is
1.
Bit 7: ICE
Description
0
Interface module disabled, with SCL and SDA signals in high-impedance state
(Initial value)
1
Interface module enabled for transfer operations (pins SCL and SDA are
driving the bus*)
Note: * Pin SDA is multiplexed with the WAIT input pin. In expanded mode, WAIT input has priority
for this pin.
Bit 6—I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C
bus interface to the CPU.
Bit 6: IEIC
Description
0
1
Interrupts disabled
Interrupts enabled
(Initial value)
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I2C bus interface operates in master mode or slave mode.
TRS selects whether the I2C bus interface operates in transmit mode or receive mode.
In master mode, when arbitration is lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. In slave receive mode with the addressing format (FS = 0),
hardware automatically selects transmit or receive mode according to the R/W bit in the first byte
after a start condition.
MST and TRS select the operating mode as follows.
Bit 5: MST
Bit 4: TRS
Operating Mode
0
0
1
0
1
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
(Initial value)
1
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HITACHI [ HITACHI SEMICONDUCTOR ]
