13.2.5 I2C Bus Status Register (ICSR)
Bit
7
BBSY
0
6
IRIC
0
5
SCP
1
4
—
1
3
AL
2
AAS
0
1
ADZ
0
0
ACKB
0
Initial value
Read/Write
0
R/W
R/(W)*
W
—
R/(W)*
R/(W)* R/(W)*
R/W
Note: * Only 0 can be written, to clear the flag.
ICSR is an 8-bit readable/writable register with flags that indicate the status of the I2C bus
interface. It is also used for issuing start and stop conditions, and recognizing and controlling
acknowledge data.
ICSR is initialized to H'30 by a reset and in hardware standby mode.
Bit 7—Bus Busy (BBSY): This bit can be read to check whether the I2C bus (SCL and SDA) is
busy or free. In master mode this bit is also used in issuing start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, use a MOV instruction to
write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode.
Bit 7: BBSY
Description
0
Bus is free
(Initial value)
This bit is cleared when a stop condition is detected.
Bus is busy
1
This bit is set when a start condition is detected.
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HITACHI [ HITACHI SEMICONDUCTOR ]
