Bit 6—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface
has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a
slave address or general call address is detected in slave receive mode, and when bus arbitration is
lost in master transmit mode. IRIC is set at different timings depending on the ACK bit in ICCR
and WAIT bit in ICMR. See the item on IRIC Set Timing and SCL Control in section 13.3.6
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
Bit 6: IRIC
Description
0
Waiting for transfer, or transfer in progress
(Initial value)
To clear this bit, the CPU must read IRIC when IRIC = 1, then write 0 in IRIC
1
Interrupt requested
This bit is set to 1 at the following times:
Master mode
•
•
End of data transfer
When bus arbitration is lost
Slave mode (when FS = 0)
•
When the slave address is matched, and whenever a data transfer ends at
the timing of a retransmit start condition after address matching or a stop
condition is detected
•
When a general call address is detected, and whenever a data transfer
ends at the timing of a retransmit start condition after address detection or a
stop condition is detected
Slave mode (when FS = 1)
End of data transfer
•
Bit 5—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A start
condition for retransmit is issued in the same way. To issue a stop condition, write 0 in BBSY and
0 in SCP. This bit always reads 1. Written data is not stored.
Bit 5: SCP
Description
0
1
Writing 0 issues a start or stop condition, in combination with BBSY
Reading always results in 1
Writing is ignored
(Initial value)
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
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HITACHI [ HITACHI SEMICONDUCTOR ]
