HMP8112
TABLE 28. OUTPUT FORMAT CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 16
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
1
Vertical Pixel Siting When this bit is cleared (‘0’) the chrominance pixels have a 1/2 line pixel offset from their
associated luminance pixel in a 4:2:2 subsampled scheme. When this bit is set (‘1’) the
pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. The
bit is cleared by a RESET.
0
B
0
Not Used
Write Ignored, Read 0’s
X
TABLE 29. SOFTWARE RESET AND VIDEO STATUS REGISTER
DESTINATION ADDRESS = 17
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
2
7
Software Reset
When this bit is set to 1, the entire device except the I C bus is reset to a known state
exactly like the RESET input. The software reset will initialize all register bits to their reset
state as well as place the PLLs back at the power-up state. Once set this bit is self clear-
ing after only 4 CLK periods. This bit is cleared on power-up by the external RESET pin.
0
B
6
5
Black Screen
This flag when set (‘1’) will set the output video to black when a lost vertical sync has
been detect. This flag is cleared after a RESET.
Read Only
Read Only
Line Locked Flag
This flag when set (‘1’) indicates that the Line Locked-Phase Locked Loop has locked to
the video data. The state of this flag is reflected on the LOCKED output pin. This flag is
cleared after a RESET of Software Reset.
4
Standard Error Flag This flag when set (‘1’) indicates that the Standard detected does not match the one se- Read Only
lected in the Video Input Control Register. The standard is checked against a line count
and if the line count is significantly different than the expected value then this flag is trig-
gered. The state of this flag is reflected on the STANDARD_ERROR output pin. This flag
is cleared after a RESET or Software Reset.
3 - 0
Not Used
Write ignored, Read 0’s.
TABLE 30. RESERVED
DESTINATION ADDRESS = 18
XXXX XX
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7 - 0
Reserved Read
Only
This register is reserved for future use. This register will read all zero’s and is write ig-
nored.
0000 0000
B
TABLE 31. RESERVED
DESTINATION ADDRESS = 19
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7 - 6
Reserved Read
Only
This register is reserved for future use. This register will read all zero’s and is write ig-
nored.
00
B
5
Lost HSYNC
Control
This bit controls when the PLL will declare lost horizontal sync, leave track mode and re-
turn to acquisition to acquire a new HSYNC reference. This bit should be used with
VCR’s with extremely gross headswitch errors. When this bit is cleared, lost line lock is
declared after 12 missing horizontal syncs. When this bit is set, lost line lock is declared
after one missing horizontal sync and the line lock PLL will reacquire the first HSYNC is
detects. This bit is cleared by RESET.
0
B
4 - 0
Reserved Read
Only
This register is reserved for future use. This register will read all zero’s and is write ignored.
0 0000
B
20
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