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HMP8112 参数 Datasheet PDF下载

HMP8112图片预览
型号: HMP8112
PDF下载: 下载PDF文件 查看货源
内容描述: NTSC / PAL视频解码器 [NTSC/PAL Video Decoder]
分类和应用: 解码器
文件页数/大小: 40 页 / 562 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HMP8112  
TABLE 11. COLOR SATURATION ADJUST FACTOR  
DESTINATION ADDRESS = 05  
H
BIT  
NUMBER  
RESET  
STATE  
FUNCTION  
DESCRIPTION  
7 - 0  
Color Saturation  
Adjust Factor  
This register sets the color saturation adjust factor. This value is multiplied by the chromi-  
nance (CbCr) data and allows the data to be scaled from 0 to a factor of +1.96875. This 8-bit  
number is a fractional number as shown below:  
1001 1101  
B
0
-1 -2 -3 -4 -5 -6 -7  
2
2
2
2
2
2
2
2
The contrast factor is applied after the brightness.  
TABLE 12. PHASE LOCKED LOOP CHROMINANCE SUBCARRIER TO BUS CLOCK FREQUENCY RATIO  
DESTINATION ADDRESS = 06  
H
BIT  
NUMBER  
RESET  
STATE  
FUNCTION  
DESCRIPTION  
7 - 0  
Chroma PLL Ratio  
These bits are used to program the ratio of the incoming video chrominance color sub- 1100 0001  
carrier frequency to the BUS Clock used. This number serves as the reference frequency  
of the chrominance PLL and must be very accurate. This is the lower byte of the ratio and  
encompasses the following range:  
B
-9 -10 -11 -12 -13 -14 -15 -16  
2
2
2
2
2
2
2
2
The default value is for a CLK frequency of 27MHz and a color subcarrier of 3.579545  
MHz.  
TABLE 13. PHASE LOCKED LOOP CHROMINANCE SUBCARRIER TO BUS CLOCK FREQUENCY RATIO  
DESTINATION ADDRESS = 07  
H
BIT  
NUMBER  
RESET  
STATE  
FUNCTION  
DESCRIPTION  
15 - 8  
Chroma PLL Ratio  
These bits are used to program the ratio of the incoming video chrominance color sub- 1000 0111  
carrier frequency to the BUS Clock used. This number serves as the reference frequency  
of the chrominance PLL and must be very accurate. This is the upper byte of the ratio  
and encompasses the following range:  
B
-1 -2 -3 -4 -5 -6 -7 -8  
2
2
2
2
2
2
2
2
TABLE 14. HORIZONTAL AGC START TIME REGISTER  
DESTINATION ADDRESS = 08  
H
BIT  
NUMBER  
RESET  
STATE  
FUNCTION  
DESCRIPTION  
This register provides a programmable delay for the HAGC pulse that control the sync  
7 - 0  
Horizontal AGC  
0011 1111  
B
Pulse Programmable tip AGC in the A/D converters. The start time of the HAGC pulse is set from the detection  
Start Time  
of horizontal sync in the video data. HAGC is programmable in CLK increments and has  
a fixed 1 clock delay following the falling edge of horizontal sync. This is the lower byte  
of the 10-bit word.  
TABLE 15. HORIZONTAL AGC START TIME REGISTER  
DESTINATION ADDRESS = 09  
H
BIT  
NUMBER  
RESET  
STATE  
FUNCTION  
Not Used  
DESCRIPTION  
15 - 10  
Write Ignored, Read 0’s.  
XXXX XX  
16  
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