HMP8112
TABLE 25. DC RESTORE START TIME REGISTER
DESTINATION ADDRESS = 13
H
BIT
NUMBER
RESET
STATE
FUNCTION
Not Used
DC Restore
DESCRIPTION
15 - 10
9 - 8
XXXX XX
This register provides a programmable delay for the internal DC RES signal. The start
00
B
Programmable Start time of the DC RES pulse is set from the detection of horizontal sync in the video data.
Time
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
TABLE 26. DC RESTORE END TIME REGISTER
DESTINATION ADDRESS = 14
H
BIT
NUMBER
RESET
STATE
FUNCTION
DC Restore
DESCRIPTION
7 - 0
This register provides a programmable delay for the internal DC RES signal. The end
0101 0010
B
Programmable End time of the DC RES pulse is set from the detection of horizontal sync in the video data.
Time
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
TABLE 27. DC RESTORE END TIME REGISTER
DESTINATION ADDRESS = 15
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
15 - 10
9 - 8
Not Used
XXXX XX
00
DC Restore
This register provides a programmable delay for the external DC RES signal. The end
B
Programmable End time of the DC RES pulse is set from the detection of horizontal sync in the video data.
Time
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
TABLE 28. OUTPUT FORMAT CONTROL REGISTER
DESTINATION ADDRESS = 16
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7
Square Pixel/ITU-R When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected.
BT601 Select
0
B
6, 5, 4
Output Field Control These bits control the field capture rate of the HMP8112. The user can select every 4th
000
B
“FLD_CONT(2-0)”
field, every other field or every field of video to be output to the data port.
000 = No Capture Enabled
001 = Capture every 4th field
010 = Capture every 2nd field
011 = Capture every 2nd odd field
100 = Capture every 2nd even field
101 = Capture every odd field
110 = Capture every even field
111 = Capture all fields
3
2
8/16 output Select
OEN
When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchro-
nous Pixel Transfer output mode is selected.
0
0
B
This bit enables the Y(7-0), CbCr(7-0), ACTIVE, HSYNC, VSYNC and DVLD outputs.
1 = Outputs enabled; 0 = three-stated.
B
19
HARRIS [ HARRIS CORPORATION ]
