HMP8112
TABLE 15. HORIZONTAL AGC START TIME REGISTER (Continued)
DESTINATION ADDRESS = 09
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
9 - 8
Horizontal AGC
This register provides a programmable delay for the HAGC pulse that control the sync
11
B
Pulse Programmable tip AGC in the A/D converters. The start time of the HAGC pulse is set from the detection
Start Time
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the upper byte
of the 10-bit word.
TABLE 16. HORIZONTAL AGC END TIME REGISTER
DESTINATION ADDRESS = 0A
H
BIT
NUMBER
RESET
STATE
FUNCTION
Horizontal AGC
DESCRIPTION
7 - 0
This register provides a programmable delay for the HAGC pulse that control the sync
0000 0000
B
Pulse Programmable tip AGC in the A/D converters. The end time of the HAGC pulse is set from the detection
End Time
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the lower byte
of the 10-bit word.
TABLE 17. HORIZONTAL AGC END TIME REGISTER
DESTINATION ADDRESS = 0B
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
15 - 10
9 - 8
Not Used
Write Ignored, Read 0’s
This register provides a programmable delay for the HAGC pulse that control the sync
XXXX XX
00
Horizontal AGC
B
Pulse Programmable tip AGC in the A/D converters. The end time of the HAGC pulse is set from the detection
End Time
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the upper byte
of the 10-bit word.
TABLE 18. HORIZONTAL SYNC START TIME REGISTER
DESTINATION ADDRESS = 0C
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7 - 0
Horizontal Drive
This register provides a programmable delay for the external HDRIVE signal. The start 0011 1011
B
Programmable Start time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
Time
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
TABLE 19. HORIZONTAL SYNC START TIME REGISTER
DESTINATION ADDRESS = 0D
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
15 - 10
9 - 8
Not Used
Write Ignored, Read 0’s
This register provides a programmable delay for the external HDRIVE signal. The start
XXXX XX
11
Horizontal Drive
B
Programmable Start time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
Time
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
17
HARRIS [ HARRIS CORPORATION ]
