HMP8112
TABLE 20. HORIZONTAL SYNC END TIME REGISTER
DESTINATION ADDRESS = 0E
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7 - 0
Horizontal Drive
This register provides a programmable delay for the external HDRIVE signal. The end
0010 0000
B
Programmable End time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
Time
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
TABLE 21. HORIZONTAL SYNC END TIME REGISTER
DESTINATION ADDRESS = 0F
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
15 - 10
9 - 8
Not Used
Write Ignored, Read 0’s
This register provides a programmable delay for the external HDRIVE signal. The end
XXXX XX
00
Horizontal Drive
B
Programmable End time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
Time
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
TABLE 22. PHASE LOCKED LOOP ADJUST REGISTER
DESTINATION ADDRESS = 10
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7 - 0
Phase Locked Loop The Phase Locked Loop time constants can be changed for testing purposes. It is rec-
0000 0000
B
Filter Adjust Test
Register
ommended that the default value of (20 ) always be used. The reset state is 00 .
H
H
TABLE 23. PHASE LOCKED LOOP SYNC DETECT WINDOW REGISTER
DESTINATION ADDRESS = 11
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
7 - 0
Phase Locked Loop These bits control the PLL horizontal sync detect window. This window sets the length
1101 1101
B
Horizontal Sync
Detect Window
of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of
this window are declared missing and will cause the missing sync logic to start counting
missing syncs. For NTSC this value should be DD and for PAL, FF .
H
H
TABLE 24. DC RESTORE START TIME REGISTER
DESTINATION ADDRESS = 12
H
BIT
NUMBER
RESET
STATE
FUNCTION
DESCRIPTION
This register provides a programmable delay for the internal DC RES signal. The start
7 - 0
DC Restore
0011 0111
B
Programmable Start time of the DC RES pulse is set from the detection of horizontal sync in the video data.
Time
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
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HARRIS [ HARRIS CORPORATION ]
