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HMP8112 参数 Datasheet PDF下载

HMP8112图片预览
型号: HMP8112
PDF下载: 下载PDF文件 查看货源
内容描述: NTSC / PAL视频解码器 [NTSC/PAL Video Decoder]
分类和应用: 解码器
文件页数/大小: 40 页 / 562 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HMP8112  
Absolute Maximum Ratings  
Thermal Information  
o
Digital Supply Voltage (V  
to DGND) . . . . . . . . . . . . . . . . . . .7.0V  
Thermal Resistance (Typical, See Note 1)  
θ
( C/W)  
CC  
Digital Input Voltages . . . . . . . . . . . . . . . . . GND -0.5V to V  
JA  
0.5V  
CC  
PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Maximum Power Dissipation  
42  
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1  
HMP8112CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9W  
o
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Operating Temperature Range  
o
Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C  
o
o
HMP8112CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C  
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air. Dissipation rating assumes device is mounted with  
JA  
all leads soldered to printed circuit board  
o
Electrical Specifications  
V
= 5.0V, T = 25 C  
A
CC  
HMP8112C  
TYP  
PARAMETER  
SYMBOL  
TEST CONDITION  
MIN  
MAX  
UNITS  
POWER SUPPLY CHARACTERISTICS  
Power Supply Voltage Range  
Power Supply Current  
DV , AV  
CC  
Note 2  
= 30MHz,  
4.75  
-
5
5.25  
60  
V
CC  
Digital I  
f
45  
mA  
CCOP  
CLK  
DV  
= 5.25V,  
CC  
Outputs Not Loaded  
Analog I  
CAOP  
f
= 30MHz,  
-
-
170  
180  
mA  
W
CLK  
AV  
= 5.25V  
CC  
Total Power Dissipation  
P
f
= 30MHz,  
0.95  
1.26  
TOT  
CLK  
DV  
= AV  
= 5.25,  
CC  
CC  
Outputs Not Loaded  
DIGITAL I/O  
Bus Clock Frequency  
Clock Cycle Time  
CLK  
CLK  
Note 2  
20  
33  
40  
8
-
-
-
-
-
-
-
-
-
-
30  
50  
60  
-
MHz  
ns  
%
Clock Waveform Symmetry  
Clock Pulse Width High  
Clock Pulse Width  
t
ns  
ns  
V
PWH  
t
13  
2.8  
-
-
PWL  
Input Logic High Voltage  
Input Logic Low Voltage  
Input Leakage Current  
V
CLK  
DV  
DV  
DV  
= Max  
= Min  
= Max  
-
IH  
CC  
CC  
CC  
V
IL  
CLK  
IH  
0.8  
10  
-
V
I
-
µA  
µA  
pF  
Input = 0V or DV  
CC  
I
-400  
-
IL  
Input/Output Capacitance  
C
CLK Frequency = 1MHz,  
Note 2, All Measurements  
Referenced to Ground T = 25 C  
A
8
IN  
o
Rise/Fall Time  
t , t  
Note 2  
-
2.0  
-
-
-
-
-
2.0  
-
ns  
V
r
f
Input Logic High Voltage  
Input Logic Low Voltage  
Input Logic Current  
V
DV  
DV  
DV  
= Max  
= Min  
= Max  
IH  
CC  
CC  
CC  
V
0.8  
10  
V
IL  
I
, I  
-
µA  
IH IL  
Input = 0V or 5V  
24  
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