HMP8112
Pin Description
PQFP PIN
INPUT/
NAME
NUMBER
OUTPUT
DESCRIPTION
LIN[0:2]
5, 6, 7
Input
Analog Video Inputs. Inputs 0 and 1 are composite inputs. Input 2 can be either a
composite input or the Y component of an S-Video signal.
CIN
19
27
Input
Input
Analog Chroma input component of an S-Video Input.
WPE
White Peak Enable. When enabled (‘1’), the video amplifiers gain is reduced when
the digital output code exceeds 248. When disabled (‘0’) the video amplifier will clip
when the A/D reaches code 255.
GAIN_CTRL
DEC_T
28
78
Input
Input
Gain Control Input. DC voltage to set the video amplifier’s gain.
Decoupling for A/D Converter Reference. Connect a 0.01µF and 0.1µF capacitors to
AGND.
DEC_L
30
77
76
29
Input
Input
Input
Input
Decoupling for A/D Converter Reference. Connect a 0.01µF and 0.1µF capacitors to
AGND.
LAGC_CAP
Capacitor Connection for Luminance AGC Circuit. Controls the AGC loop time con-
stant.
LCLAMP_CAP
CCLAMP_CAP
Capacitor Connection for Luminance Clamp Circuit. Controls the clamp loop time
constant.
Capacitor Connection for Chrominance Clamp Circuit. Controls the clamp loop time
constant.
L_ADIN
L_OUT
SDA
8
9
Input
Luminance A/D Converters input from antialiasing filter.
Output
Luminance or Composite Analog Video Amplifier output to antialiasing filter.
2
40
Input/
The serial I C serial input/output data line.
Output
2
SCL
CLK
41
Input
Input
The serial I C serial bus clock line.
13, 38
Master clock for the decoder. This clock is used to run the internal logic, A/D convert-
ers, and Phase Locked Loops. All I/O pins (except the I C) are synchronous to this
2
master clock. A 50ppmcrystal should be used with a waveform symmetry of 60/40%
or better.
RESET
34
Input
Asynchronous Reset pin. Master Chip reset to initialize the internal states and set
the internal registers to a known state.
CbCr[0:7]
42, 43, 45,
47-51
Output
CbCr Data Output Port. The chrominance data output port of the decoder. Data is in
unsigned format and can range from 0 to 255. The CbCr data is subsampled to 4:2:2
format. In 4:2:2 format the CbCr bus toggles between Cb and Cr samples with the
first sample of a line always being Cb. The port is designed to minimize external logic
needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
Y[0:7]
DVLD
54-58, 60, 63,
64
Output
Output
Output
Y Data Output Port. The luminance data output port of the decoder. Data is in un-
signed format and can range from 16 to 255. The port is designed to minimize exter-
nal logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
66
71
Data Valid. This pin signals when valid data is available on the data output ports. This
pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
HSYNC
Horizontal Sync. This video synchronous pulse is generated by the detection of hor-
izontal sync on the video input. In the absence of video, the HSYNC rate is set when
the internal PLL counters overflow. The HSYNC begin and end time can be pro-
grammed and is synchronous to CLK. This pin is three-stated after a RESET or soft-
ware reset and should be pulled high through a 10K resistor.
22
HARRIS [ HARRIS CORPORATION ]
