GS9090 Data Sheet
3.11 Parallel Data Outputs
Data outputs are valid on the rising edge of PCLK as shown in Figure 3-13.
tOH
t
OD
PCLK
50%
V
OH
OL
V
OH
DOUT[9:0]
VOL
V
V
OH
V
OH
CONTROL
SIGNAL OUTPUT
V
OL
V
OL
Figure 3-13: PCLK to Data & Control Signal Output Timing
The data is presented in 10-bit format and may be scrambled or unscrambled,
framed or unframed.
The output data format is defined by the settings of the external SMPTE_BYPASS
and DVB_ASI pins (see Table 3-16). Recall that in Manual mode, these pins are
set by the application layer as inputs to the device. In Auto mode, however, the
GS9090 sets these pins as output status signals.
Table 3-16: Parallel Data Output Format
Pin Settings
DVB_ASI
Output Data Format
DOUT[9:0]
SMPTE_BYPASS
10-bit Data
DATA
LOW
HIGH
LOW
LOW
LOW
HIGH
10-bit Multiplexed SD
10-bit DVB-ASI
Luma / Chroma
DVB-ASI data
3.11.1 Parallel Data Bus
The parallel data outputs of the GS9090 support both LVTTL and LVCMOS levels.
These outputs use either +1.8V or +3.3V, supplied at the IO_VDD and IO_GND
pins. When interfacing with +5V logic levels, the IO_VDD pins should be supplied
with +3.3V. For a low power connection, the IO_VDD pins may be connected to
+1.8V.
All outputs, including the PCLK output, will be driven to a high-impedance state if
the RESET signal is asserted LOW with the exception of the STAT pins and the
DATA_ERROR pin which will maintain the last state they were in for the duration
that RESET is asserted.
28201 - 1 July 2005
55 of 70
GENNUM [ GENNUM CORPORATION ]
