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GS1559_08 参数 Datasheet PDF下载

GS1559_08图片预览
型号: GS1559_08
PDF下载: 下载PDF文件 查看货源
内容描述: HD- LINX II多速率解串器,带环通电缆驱动器 [HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver]
分类和应用: 驱动器
文件页数/大小: 71 页 / 1322 K
品牌: GENNUM [ GENNUM CORPORATION ]
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The FW_EN/DIS input pin controls the synchronization mechanism of the Flywheel.  
When this input signal is LOW, the Flywheel will re-synchronize all pixel and line based  
counters on every received TRS ID word.  
When FW_EN/DIS is held HIGH, re-synchronization of the pixel and line based counters  
will only take place when a consistent synchronization error has been detected. Two  
consecutive video lines with identical TRS timing different to the current Flywheel  
timing must occur to initiate re-synchronization of the counters. This provides a  
measure of noise immunity to internal and external timing signal generation.  
The Flywheel will be disabled should the LOCKED signal or the RESET_TRST signal be  
LOW. A LOW to HIGH transition on either signal will cause the Flywheel to re-acquire  
synchronization on the next received TRS word, regardless of the setting of the  
FW_EN/DIS pin.  
4.7.3 Switch Line Lock Handling  
The principal of Switch Line Lock Handling is that the switching of synchronous video  
sources will only disturb the horizontal timing and alignment of the stream, whereas the  
vertical timing remains in synchronization.  
To account for the horizontal disturbance caused by a synchronous switch, it is  
necessary to re-synchronize the Flywheel immediately after the switch has taken place.  
Rapid re-synchronization of the GS1559 to the new video standard can be achieved by  
controlling the Flywheel using the FW_EN/DIS pin.  
At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW to HIGH  
transition at this pin is detected anywhere within the active line, the Flywheel will  
re-synchronize immediately to the next TRS word. This is shown in Figure 4-2.  
To ensure Switch Line Lock Handling, the FW_EN/DIS signal should be LOW for a  
minimum of one PCLK cycle (maximum one video line) anywhere within the active  
portion of the line on which the switch has taken place.  
GS1559 HD-LINX™ II Multi-Rate Deserializer with  
Loop-Through Cable Driver  
Data Sheet  
33 of 71  
30572 - 8  
July 2008  
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