GL9701 PCI ExpressTM to PCI Bridge
Byte Offset
Bit31
0
Device ID
Status
Vendor ID
Command
00h
04h
08h
0Ch
Class Code
Header Type
Revision ID
BIST
Primary
Cache Line Size
Latency Timer
Base Address Register 0
Base Address Register 1
10h
14h
18h
Secondary
Subordinate Secondary Bus
Primary Bus
Number
Latency timer Bus Number
Secondary Status
Number
I/O Limit
I/O Base
1Ch
20h
Type1 Header
Memory Limit
Memory Base
Prefetchable Memory Base
Prefetchable Memory Limit
24h
28h
2Ch
30h
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
Reserved
Capabilities Pointer 34h
38h
Expansion ROM Base Address
Bridge Control
Interrupt Pin
Interrupt Line
PCI Express
Cap ID
3Ch
PCI Express Capabilities
Register
Next Cap Pointer
70h
Device Capabilities
Link Capabilities
Reserved
74h
78h
7Ch
80h
84h
88h
8Ch
90h
PCI Express
Capability
Device Status
Link Status
Device Control
Link Control
Reserved
Reserved
Reserved
Reserved
Reserved
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Page 32
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