GL9701 PCI ExpressTM to PCI Bridge
The operational frequency of these PCI clocks can be configured by M66EN (PIN40). When it’s set to high,
then the PCI clocks will operate at 66MHz. When it’s set to low, then these clocks will operate at 33MHz.
The six clock output are at GLIO0 ~ GPIO5. It’s recommended that GPIO0 be connected to PCICLKI
(PIN110) to feed GL9701 itself. GPIO1 ~ GPIO5 then can be distributed to the five PCI slots. Users may
optionally implement the number of PCI slots greater than one and less than five. Users can even use an
external PCI clock source to maintain the normal operation of GL9701 and its secondary PCI slots.
If not all the five PCI slots are utilized, users can use the GPIOx (x=1~5, 0 is valid when an external PCI clock
source is provided) for the use of General Purpose I/O. The optional use between PCI clock source and GPIO
can be determined by the PCICLK_MASKx (x=0~5).
When PCICLK_MASKx (x=0~5) is set, the PCI clock output of the corresponding GPIOx is masked. The
GPIOx then becomes a General Purpose I/O. Users then can arbitrarily specify the output enable control
(GPIOx_OE) and the output value (GPIOxO) for the GPIOx.
GL9701 also provides a General Purpose I/O , GPIO6 (PIN65), for users to use. Unlike GPIO0~GPIO5, this
pin does not Mux other functions. Users just have to control the output enable (GPIO6_OE) and its output
value (GPIO6O).
5.4 Interrupt mapping
PCI INTx interrupts are “virtualized” in PCI Express using Assert_INTx and Deassert_INTx
messages, where x is A, B, C, and D for the respective PCI INTx# interrupt signals defined in
PCI 3.0. This message pairing provides a mechanism to preserve the level-sensitive semantics of the PCI
interrupts. The Assert_INTx and Deassert_INTx messages transmitted on the PCI Express Link capture the
asserting/deasserting edge of the respective PCI INTx# signal.
GL9701 is a multi-ported PCI Express bridge. A multi-ported PCI Express bridges must collapse the
INTA#-INTD# pins from each of their downstream conventional PCI interface into four INTx “virtual wires” on
their Upstream Port. The mapping between the INTx# pin on a PCI bus and the corresponding INTx messages
on the PCI Express Link is based on the device number of the PCI bridge assigned to the port requesting the
interrupt. The mapping is as follows:
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