GL9701 PCI ExpressTM to PCI Bridge
The GL9701 is composed of the following major functional blocks as shown in Figure 3-1:
·
PCI interface macro
The macro acts as either a bus master or a bus slave and handles the PCI protocol depending on the
transaction types. GL9701 supports 32-bit PCI addressing with 0MHz~33MHz and 66MHz operation
frequency.
Table3.1 summarizes the PCI commands supported by GL9701
Command Type
I/O Read
Encoding
0010
I/O Write
0011
Memory Read
Memory Write
0110
0111
1010
1011
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
1100
1110
Memory Write and
Invalidate
1111
Table 4.1－Supported PCI Command
·
·
·
·
Bus Arbiter
This block supports PCI bus arbiter for secondary PCI bus. The bus arbitration is provided by GL9701
and supports up to five external masters. The arbiter can be disabled by external EEPROM.
Configuration Registers
This module supports two mechanisms for configuration space access: PCI compatible and PCI Express
enhanced configuration mechanism.
Power Management
The moudle is in charge of power management event signaling. This module enables GL9701 to enter
software driven D-state transitions.
Transaction Translator
The Transaction Translator manages all the bridge operation between PCI Express and PCI interface. It
is responsible for PCI Express to PCI command translation, message translation and managing
transaction ordering.
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