GL9701 PCI ExpressTM to PCI Bridge
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PCI Express Transaction Layer
The layer’s function is the assembly and disassembly of Transaction Layer Packets (TLPs). It is also
responsible for managing credit-based flow control for TLPs.
PCI Express Data Link Layer
The layer serves as an intermediate stage between the Transaction Layer and the Physical Layer. The
responsibility is Link management and data integrity including error detection and error correction.
PCI Express MAC Layer
The Layer can be taken as a part of Physical Layer. It includes link initialization, link state management,
lane alignment, data scrambling and descrambling.
PCI Express x1 PHY
The PHY includes all circuitry for interface operation for an x1 link, including driver and input buffers,
parallel-to-serial and serial-to-parallel conversion, PLL(s) and impedance matching circuitry. It also
includes logical function related to 8b/10b encoding/decoding and PHY status report.
SMBus Slave
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The SMBus Slave handles SMBus protocol and provides the access to internal registers such as chip
information, function options and some test setting.
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EEC, EERPOM Controller
Provide a download path for chip configuration and information.
Clocking/Reset
Provide a clocking and reset to manage all blocks.
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