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GL9701-MXG 参数 Datasheet PDF下载

GL9701-MXG图片预览
型号: GL9701-MXG
PDF下载: 下载PDF文件 查看货源
内容描述: PCI ExpressTM至PCI桥 [PCI ExpressTM to PCI Bridge]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路PC
文件页数/大小: 75 页 / 1051 K
品牌: GENESYS [ GENESYS LOGIC ]
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GL9701 PCI ExpressTM to PCI Bridge  
CHAPTER 5 Function Description  
5.1 Power Management  
GL9701 supports PCI-PM 1.1 Compatible Power Management and Active State Power Management (ASPM)  
defined in PCI Express Base Specification Revision 1.0a.  
5.1.1 PCI-PM Software Compatible Power Management  
GL9701 supports link states L0, L1 and L2 needed to implement PCI-PM compatible power states D0, D1, D2  
and D3hot. All link states are determined by the D-state of the bridge. Because GL9711 provides Vaux, bridge  
will enter into L2 state when software direct bridge into D3hot state. Refer to the PCI Express Base  
Specification Revision 1.0a for more protocol information involved in transitioning the link to the L1 or L2  
state.  
5.1.2 Hardware-Controlled Active State Power Management  
GL9701 supports a hardware-initiated power management mechanism which is called Active State Power  
Management (ASPM). Once this feature is enabled, bridge will drive the link state into a low-power L0s link  
state or even lower-power L1 link state. Refer to the PCI Express Base Specification Revision 1.0a for more  
information about ASPM.  
Once system software enables GL9701s ASPM capability by setting the ASPM Control bit of Link Control  
Register to high, GL9701 will behavior ASPM specified in PCI Express Base Specification Revision 1.0a by  
default. However, GL9701 can disable this mechanism via the optional setting specified in table6.1. The  
optional bit is the 30th bit of Configuration Space Register with offset hc8. If this bit is set to low, then  
GL9701 will never act ASPM behavior no matter what value of the ASPM Control bit of Link Control  
Register.  
5.1.3 In-band Beacon  
Beacon is a in-band signal used to exit the L2 link power management state and informs the Root Complex to  
re-activate the link. When the bridge is directed into D3hot State, the link state will finally stay in L2 State.  
The device on the secondary PCI bus wakes up the system by asserting PME_N. GL9701 then outputs the  
beacon signal on the upstream PCI Express link. Root complex should re-apply the power and reference  
clock again after detecting the beacon.  
©2000-2006 Genesys Logic Inc. - All rights reserved.  
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