GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 6 Register Description
GL9701 implements the standard PCI Express-to-PCI Bridge configuration space format. Figure5.1 shows the
capabilities supported by GL9701. Table5.1 and Table5.2 represent the configuration registers of GL9701 and
their address byte offset values.
Configuration register fields are assigned one of the attributes described in Table5.1.
Register Attribute
HwInit
Description
Hardware Initialized: Register bits are initialized by
firmware or hardware mechanisms such as pin strapping or
serial EEPROM. Bits are read-only after initialization and can
only be reset (for write-once by firmware) with Fundamental
Reset.
RO
Read-only register: Register bits are read-only and cannot be
altered by software. Register bits may be initialized by
hardware mechanisms such as pin strapping or serial
EEPROM.
RW
Read-Write register: Register bits are read-write and may be
either set or cleared by software to the desired state.
Read-only status, Write-1-to-clear status register: Register
bits indicate status when read, a set bit indicating a status
event may be cleared by writing a 1. Writing a 0 to RW1C
bits has no effect.
RW1C
ROS
RWS
Sticky – Read-only register: Registers are read-only and
cannot be altered by software. Registers are not initialized or
modified by hot reset.
Sticky – Read-Write register: Registers are read-write and
may be either set or cleared by software to the desired state.
Bits are not initialized or modified by hot reset.
Sticky – Read-only status, Write-1-to-clear status register:
Registers indicate status when read, a set bit indicating a
status event may be cleared by writing a 1. Writing a 0 to
RW1CS bits has no effect. Bits are not initialized or modified
by hot reset.
RW1CS
RsvdP
Reserved and Preserved: Reserved for future RW
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