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GL9701-MXG 参数 Datasheet PDF下载

GL9701-MXG图片预览
型号: GL9701-MXG
PDF下载: 下载PDF文件 查看货源
内容描述: PCI ExpressTM至PCI桥 [PCI ExpressTM to PCI Bridge]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路PC
文件页数/大小: 75 页 / 1051 K
品牌: GENESYS [ GENESYS LOGIC ]
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GL9701 PCI ExpressTM to PCI Bridge  
INTD_N  
PME_N  
I
Power management event from secondary interface  
WAKE_N  
OD  
Used to implement wakeup mechanism.  
3.4.3 EEPROM Signals  
Name  
PROMCS  
Type  
Description  
Enable EEPROM interface  
O
O
I
PROMDO  
PROMDI  
PROMSK  
Serial data output for EEPROM  
Serial data input from EEPROM  
Serial clock output for EEPROM  
O
3.4.4 Miscellaneous Signals  
Name  
Type  
Description  
GPIO[6:0]  
TS  
The output signals are determined by OPMODE[1:0],  
PCICLKx_MASK(x=0~5) in design option.  
For GPIO[2:0]:  
Available only in normal mode. (OPMODE[1:0]=2b00)  
If PCICLKx_MASK (x=0~2) are not masked (=1b0), then  
these three bits are used as PCI clock outputs. Its recommended  
that GPIO[0] be routed to PCICLKI input.  
If PCICLKx_MASK (x=0~2) are masked (=1b1) then these  
three bits are used as output of GPIO signal from design option.  
For GPIO[5:3]:  
If in normal function mode (OPMODE[1:0]=2b00), then these  
three bits are used as PCI clock outputs when  
PCICLKx_MASK(x=5~3) are not masked (=1b0). These three  
bits are used as GPIO output from design option if  
PCICLKx_MASK(x=5~3) are masked (=1b1).  
If in test mode (OPMODE[1:0]=2b01), then these three bits are  
used as internal signal output.  
For GPIO[6]:  
If in normal function mode (OPMODE[1:0]=2b00), the bit is  
used as GPIO pins. Users can specify the output value and  
©2000-2006 Genesys Logic Inc. - All rights reserved.  
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