GL9701 PCI ExpressTM to PCI Bridge
output enable via design option. Users can also probe the input
value by reading the design option.
▪ If in normal function (OPMODE[1:0]=2’b01), then this bit is
used as internal signal output.
OPMODE[1:0]
TESTC
I
Operation mode setup
I
Test clock
TESTD
TS
TS
Test data
CLKRUN_N
A PCI device can request GL9701 to start, speed up, or maintain the
PCI clock by the assertion of CLKRUN_N. GL9701 is responsible
for maintaining CLKRUN_N asserted, and for driving it high to the
de-asserted state.
CLKRUN_N_E
N
I
I
Clock Run Enable
1’b1: Enable Clock Run
1’b0: Disable Clock Run
M66EN
Enable PCI clock act as 33MHz or 66MHz.
1: PCI Clocks are 66MHz.
0: PCI clocks are 33MHz
3.4.5 Power and Ground Signals
Name
VSS33
Type
P
Description
Ground for PCI PAD
VDD33
P
3.3V Power Supplier for PCI PAD
Ground for 1.8 Vaux
VSS18_AUX
VDD18_AUX
VSS33_AUX
VDD33_AUX
VSS18
P
P
1.8Vaux Power Supplies for core voltage
Ground for 3.3 Vaux
P
P
3.3Vaux Power Supplies for core voltage
Digital ground
P
VDD18
P
1.8V Power Supplies for core voltage
Ground for the guard ring of the SerDes block
1.8V Power Supplies for internal PLL
Ground for internal PLL
VSSGR
P
VDDPLL
VSSPLL
P
P
VSSRX
P
1.8V Power Supplies for receiver part
VDDRX
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