MB90560/565 Series
(2) UART structure
The UART consists of the following 11 blocks:
• Clock selector
• Mode registers (SMR0, SMR1)
• Control registers (SCR0, SCR1)
• Status registers (SSR0, SSR1)
• Input data registers (SIDR0, SIDR1)
• Output data registers (SODR0, SODR1)
• Receive control circuit
• Transmission control circuit
• Receive status evaluation circuit
• Receive shift register
• Transmission shift register
• Block diagram
Control bus
Receive
interrupt signal
#39 (27H)*
<#37 (25H)*>
Dedicated baud
rate generator
Transmit clock
Clock
Transmit
16-bit reload timer
selector
interrupt signal
#40 (28H)*
<#38 (26H)*>
Receive
clock
Transmission
control circuit
Receive
control circuit
Pin
Start bit
detection circuit
Transmission
start circuit
P40/SCK0
<P62/SCK1>
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P37/SOT0
<P61/SOT1>
Receive
shift register
Transmission
shift register
Pin
P36/SIN0
<P60/SIN1>
Receive
Transmission start
complete
SIDR0/SIDR1
SODR0/SODR1
Receive status
evaluation circuit
Receive error detection
signal for EI2OS
(to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
PEN
P
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
SBL
CL
A/D
REC
RXE
TXE
SMR0/SMR1
SCR0/SCR1
SSR0/SSR1
SCKE
SOE
TIE
* : Interrupt number
45
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