欢迎访问ic37.com |
会员登录 免费注册
发布采购

MB90F562 参数 Datasheet PDF下载

MB90F562图片预览
型号: MB90F562
PDF下载: 下载PDF文件 查看货源
内容描述: 16位微控制器专用 [16-bit Proprietary Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 91 页 / 879 K
品牌: FUJITSU [ FUJITSU ]
 浏览型号MB90F562的Datasheet PDF文件第43页浏览型号MB90F562的Datasheet PDF文件第44页浏览型号MB90F562的Datasheet PDF文件第45页浏览型号MB90F562的Datasheet PDF文件第46页浏览型号MB90F562的Datasheet PDF文件第48页浏览型号MB90F562的Datasheet PDF文件第49页浏览型号MB90F562的Datasheet PDF文件第50页浏览型号MB90F562的Datasheet PDF文件第51页  
MB90560/565 Series  
7. DTP/External Interrupt Circuit  
(1) Overview of the DTP/external interrupt circuit  
The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input to the external  
interrupt input pins (INT7 to INT0) and outputs interrupt requests.  
DTP/external interrupt circuit functions  
The DTP/external interrupt function detects edge or level signals input to the external interrupt input pins (INT7  
to INT0) and outputs interrupt requests.  
The interrupt request is received by the CPU and, if the extended intelligent I/O service (EI2OS) is enabled,  
EI2OS performs automatic data transfer (DTP function) then passes control to the interrupt handler routine on  
completion. If EI2OS is disabled, control passes directly to the interrupt handler routine without performing  
automatic data transfer (DTP function) .  
Overview of the DTP/external interrupt circuit  
External Interrupt  
DTP Function  
Input pins  
8 channels (P10/INT0 to P16/INT6, P63/INT7)  
The level or edge to detect can be set independently for each pin in the detection lev-  
el setup register (ELVR) .  
Interrupt conditions  
“L” level, “H” level, rising edge, or falling edge input  
#25 (19H) to #28 (1CH)  
Interrupt number  
Interrupt control  
Interrupts can be enabled or disabled in the DTP/external interrupt enable register  
(ENIR) .  
Interrupt flag  
The DTP/external interrupt request register (ENRR) stores interrupt requests.  
Processing selection  
Set EI2OS to disabled (ICR : ISE = 0)  
Set EI2OS to enabled (ICR : ISE = 1)  
Jumps to interrupt handler routine after  
automatic data transfer by EI2OS com-  
pletes.  
Operation  
Jumps to interrupt handler routine  
ICR : Interrupt control register  
DTP/external interrupt circuit interrupts and EI2OS  
Interrupt Control Register  
Interrupt  
Vector Table Address  
2
Channel  
No.  
EI OS  
RegisterName  
Address  
Lower  
Upper  
Bank  
INT0/INT1  
INT2/INT3  
INT4/INT5  
INT6/INT7  
#25 (19H)  
#26 (1AH)  
#27 (1BH)  
#28 (1CH)  
FFFF98H  
FFFF94H  
FFFF90H  
FFFF8CH  
FFFF99H  
FFFF95H  
FFFF91H  
FFFF8DH  
FFFF9AH  
FFFF96H  
FFFF92H  
FFFF8EH  
ICR07  
0000B7H  
ICR08  
0000B8H  
: Available when the interrupt shared with ICR07 or ICR08 is not used.  
47  
 复制成功!