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MB90F562 参数 Datasheet PDF下载

MB90F562图片预览
型号: MB90F562
PDF下载: 下载PDF文件 查看货源
内容描述: 16位微控制器专用 [16-bit Proprietary Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 91 页 / 879 K
品牌: FUJITSU [ FUJITSU ]
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MB90560/565 Series  
8. Delayed Interrupt Generation Module  
• The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this  
hardware interrupt can be specified by software.  
Delayed interrupt generation module functions  
Function and Control  
• Writing “1” to bit R0 of the delayed interrupt request generation/clear register  
(DIRR : R0 = 1) generates an interrupt request.  
• Writing “0” to bit R0 of the delayed interrupt request generation/clear register  
Interrupt trigger  
(DIRR : R0 = 1) clears the interrupt request.  
Interrupt control  
Interrupt flag  
• No enable/disable register is provided for this interrupt.  
• Set in bit R0 of the delayed interrupt request generation/clear register  
(DIRR : R0) .  
EI2OS support  
• Not supported by the extended intelligent I/O service (EI2OS) .  
Block diagram  
Internal data bus  
R0  
S
R
Interrupt  
request signal  
Interrupt request  
latch  
Delayed interrupt request generation/  
clear register (DIRR)  
: Undefined  
49  
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