MB90560/565 Series
• Clock selector
Selects the send/receive clock from either the dedicated baud rate generator, external input clock (clock input
to SCK0 or SCK1 pin) , or internal clock (clock supplied by 16-bit reload timer) .
• Receive control circuit
The receive control circuit consists of a receive bit counter, start bit detection circuit, and receive parity counter.
The receive bit counter counts the received data bits and outputs a receive interrupt request when the required
number of data bits have been received. The start bit detection circuit detects the start bit on the serial input
signal. On detecting a start bit, the receive data is shifted to the input data register (SIDR0 or SIDR1) in
accordance with the specified transfer speed. The receive parity counter calculates the parity of the received
data if parity is selected.
• Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission
parity counter. The transmission bit counter counts the transmitted data bits and outputs a transmit interrupt
request when the required number of data bits have been sent. The transmission start circuit starts transmission
when data is written to the output data register (SODR0 or SODR1) . The transmission parity counter generates
the parity bit for the transmitted data when parity is selected.
• Receive shift register
The receive shift register captures the data input from the SIN0 or SIN1 pin by shifting one bit at a time then
transfers the received data to the input data register (SIDR0 or SIDR1) when reception completes.
• Transmission shift register
The transmission data is transferred from the output data register (SODR0 or SODR1) to the transmission shift
register and output from the SOT0 or SOT1 pin by shifting one bit at a time.
• Mode register (SMR0, SMR1)
Set the operation mode, baud rate clock and serial clock input/output control, and enables output for the
serial data pin.
• Control register (SCR0, SCR1)
Specifies whether to use parity, the type of parity, number of stop bits and data bits and the frame data format
for operation mode 1, to clear the receive error flag bit, and to enable or disable send and receive operation.
• Status register (SSR0, SSR1)
Stores the send/receive and error status information, set the serial data transfer direction, and enables or disables
the send and receive interrupt requests.
• Input data register (SIDR0, SIDR1)
Stores the received data.
• Output data register (SODR0, SODR1)
Set the transmission data. The data set in the output data register is converted to serial format and output.
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FUJITSU [ FUJITSU ]
