MB90560/565 Series
• UART operation modes
No. of Data Bits
No Parity With Parity
7 or 8 bits
Operation Mode
Synchronization
No. of Stop Bits
0
1
2
Normal mode
Asynchronous
Asynchronous
Synchronous
1 or 2 bits*2
None
Multi-processor mode
Clock synchronous mode
8 + 1*1
8
: Not available
*1 : The “+1” represents the address/data (A/D) bit used for communication control.
*2 : Only 1 stop bit supported for receiving.
• UART interrupts and EI2OS
Interrupt Control
Vector Table Address
Register
Interrupt
No.
2
Interrupt
EI OS
Register
Name
Address
0000BDH
0000BDH
0000BEH
0000BEH
Lower
Upper
Bank
UART1
receive interrupt
#37 (25H)
#38 (26H)
#39 (27H)
#40 (28H)
ICR13
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF69H
FFFF65H
FFFF61H
FFFF5DH
FFFF6AH
FFFF66H
FFFF62H
FFFF5EH
UART1
send interrupt
ICR13
ICR14
ICR14
UART0
receive interrupt
UART0
send interrupt
: The UART has a function to halt EI2OS if a receive error is detected.
: Available when the interrupt shared with ICR13 or ICR14 is not used.
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