MB90560/565 Series
• Block diagram
• 16-bit freerun timer, input capture, and output compare
To interrupt
#31 (1FH)
φ
*
3
8
IVF
IVFE STOP MODE SCLR CLK2
16-bit freerun timer
CLK1 CLK0
Divider
Clock
16
16
To interrupt
#34 (22H)
16-bit compare clear register
Compare registers 0, 2, 4
Compare circuit
*
MS13 to 0
ICLR
ICRE
To A/D trigger
T
Q
Q
Compare circuit
To RT0, 2, 4
waveform generator
16
4
Compare registers 1, 3, 5
CMOD
To RT1, 3, 5
waveform generator
T
Compare circuit
IOP1
IOP0
IOE1
IOE0
To interrupts
#13 (0DH) *, #17 (11H) *,
#21 (15H) *
#15 (0FH) *, #19 (13H) *,
#23 (17H) *
Capture registers 0, 2
Edge detection
IN0/2
4
4
EG11 EG10
EG01 EG00
IN1/3
Capture registers 1, 3
Edge detection
ICP0
ICP1
ICE0
ICE1
To interrupts
#33 (21H) *, #35 (23H) *
#33 (21H) *, #35 (23H) *
* : Interrupt number
φ : Machine clock frequency
40
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