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V2DIP1-48 参数 Datasheet PDF下载

V2DIP1-48图片预览
型号: V2DIP1-48
PDF下载: 下载PDF文件 查看货源
内容描述: 设计,让使用VNC2-48Q IC设计快速发展 [Designed to allow rapid development of designs using the VNC2-48Q IC]
分类和应用:
文件页数/大小: 25 页 / 958 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document Reference No.: FT_000236
V2DIP1-48 VNC2-48 Development Module Datasheet Version 1.01
Clearance No.: FTDI# 153
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Table 3.6 - Data and Control Bus Signal Mode Options – SPI Master
3.7 Parallel FIFO Interface-Asynchronous Mode
The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface present in
VDIP1 has an eight bit parallel data bus, individual read and write strobes and two hardware flow control
signals.
3.7.1 Signal Description - Parallel FIFO Interface
The Parallel FIFO Interface signals can be programmed to a choice of available I/O pins.
shows the Parallel FIFO Interface signals and the pins that they can be mapped.
Available Pins
Name
Type
Description
J1-6, J1-11, J2-5, J2-10
fifo_data[0]
I/O
I/O
FIFO data bus Bit 0
J1-2, J1-8, J1-12, J2-9
fifo_data[1]
fifo_data[2]
fifo_data[3]
fifo_data[4]
fifo_data[5]
fifo_data[6]
fifo_data[7]
I/O
I/O
I/O
I/O
I/O
I/O
FIFO data bus Bit 1
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
J1-6, J1-11, J2-5, J2-10
J1-2, J1-8, J1-12, J2-9
FIFO data bus Bit 2
FIFO data bus Bit 3
FIFO data bus Bit 4
FIFO data bus Bit 5
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
J1-6, J1-11, J2-5, J2-10
FIFO data bus Bit 6
FIFO data bus Bit 7
When high, do not read data from
fifo_rxf#
Output
the FIFO. When low, there is data
available in the FIFO which can be
read bystrobing RD# low, then high.
J1-2, J1-8, J1-12, J2-9
fifo_txe#
Output
When high, do not write data into the
FIFO. When low, data can be written
into the FIFO by strobing WR high,
then low.
J1-3, J1-9, J2-12, J2-8
fifo_rd#
Input
Enables the current FIFO data byte
on D0...D7 when low. Fetches the
next FIFO data byte (if available)
from the receive FIFO buffer when
RD# goes from high to low
J1-10, J2-11, J2-6
fifo_wr#
Input
Writes the data byte on the D0...D7
pins into the transmit FIFO buffer
when WR goes from high to low.
Table 3.7 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface
Copyright © 2010 Future Technology Devices International Limited
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