Document Reference No.: FT_000236
V2DIP1-48 VNC2-48 Development Module Datasheet Version 1.01
Clearance No.: FTDI# 153
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3.6 Serial Peripheral Interface (SPI)
The VNC2-48Q has one master module and two slave modules. These modules are described more fully in
a Vinculum-II datasheet please refer to:- FTDI website.
3.6.1 Signal Description - SPI Slave
The SPI Slave signals can be programmed to a choice of available I/O pins. Table 3.5 explains the
available pins for each of the SPI Slave signals.
Name
Type
Description
Available Pins
J1-6, J1-11, J2-5, J2-10
spi_s0_clk
spi_s1_clk
Input
Slave clock input
J1-2, J1-8, J1-12, J2-9
spi_s0_mosi
spi_s1_mosi
Input/Output
Master Out Slave In
Synchronous data from master to
slave
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
spi_s0_miso
spi_s1_miso
Output
Input
Master In Slave Out
Synchronous data from slave to
master
spi_s0_ss#
spi_s1_ss#
Slave chip select
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Slave
3.6.2 Signal Description - SPI Master
The SPI Master signals can be programmed to a choice of available I/O pins Table 3.6 shows the SPI
master signals and the available pins that they can be mapped.
Available Pins
Name
Type
Description
J1-6, J1-11, J2-5, J2-10
spi_m_clk
Output
SPI master clock input
J1-2, J1-8, J1-12, J2-9
J1-3, J1-9, J2-12, J2-8
spi_m_mosi
spi_m_miso
Output
Input
Master Out Slave In
Synchronous data from master to
slave
Master In Slave Out
Synchronous data from slave to
master
J1-10, J2-11, J2-6
spi_m_cs_0#
spi_m_cs_1#
Output
Output
Active low slave select 0 from master
to
slave 0
Active low slave select 1 from master
to
J1-6, J1-11, J2-5, J2-10
slave 1
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