V2DIP1-48 参数 Datasheet PDF下载

Document Reference No.: FT_000236

V2DIP1-48 VNC2-48 Development Module Datasheet Version 1.01

Clearance No.: FTDI# 153

`

3.8 Parallel FIFO Interface-Synchronous Mode

The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two

hardware flow control signals, an output enable and a clock out.

The synchronous FIFO mode uses the parallel FIFO interface signals detailed in

and an

additional two signals detailed in

Available Pins

Name

Type

Description

J2-8, J2-4, J1-7,

J2-13

J1-14, J1-19, J2-18,

Output

fifo_oe#

fifo_clkout

Output

FIFO Output Enable

J2-7, J1-4, J1-8, J1-16, J1-20, J2-17

FIFO Output Enable

Table 3.9 - Data and Control Bus Signal Mode Options – Synchronous FIFO mode

3.8.1 Timing Diagram – Synchronous FIFO Mode Read and Write Cycle

When in Synchronous FIFO interface mode, the timing of a read and write operation on the FIFO interface

are shown in

and

Figure 3.5 - Synchronous FIFO Mode Read and Write Cycle

Copyright © 2010 Future Technology Devices International Limited

14