Serial RapidIO
Table 64. Receiver AC Timing Specifications—3.125 GBaud
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Differential input voltage
V
J
200
0.37
0.55
1600
—
mVp-p Measured at receiver
IN
Deterministic jitter tolerance
UI p-p
UI p-p
Measured at receiver
Measured at receiver
D
Combined deterministic and random
jitter tolerance
J
—
DR
1
Total jitter tolerance
J
0.65
—
—
UI p-p
ns
Measured at receiver
T
Multiple input skew
S
22
Skew at the receiver input between lanes
of a multilane link
MI
-12
Bit error rate
Unit interval
Note:
BER
UI
—
10
—
320
320
ps
±100 ppm
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
8.5 UI p-p
0.10 UI p-p
22.1 kHz
1.875 MHz
20 MHz
Frequency
Figure 53. Single Frequency Sinusoidal Jitter Limits
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
84
FREESCALE [ Freescale ]
