Serial RapidIO
Table 64. Receiver AC Timing Specifications—3.125 GBaud
Range
Characteristic
Differential input voltage
Deterministic jitter tolerance
Combined deterministic and random
jitter tolerance
Total jitter tolerance
1
Multiple input skew
Bit error rate
Unit interval
Symbol
Min
V
IN
J
D
J
DR
J
T
S
MI
BER
UI
200
0.37
0.55
0.65
—
—
320
Max
1600
—
—
—
22
10
-12
320
ps
±100 ppm
mVp-p
UI p-p
UI p-p
UI p-p
ns
Measured at receiver
Measured at receiver
Measured at receiver
Measured at receiver
Skew at the receiver input between lanes
of a multilane link
—
Unit
Notes
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of
The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
8.5 UI p-p
Sinusoidal Jitter Amplitude
0.10 UI p-p
22.1 kHz
Frequency
1.875 MHz
20 MHz
Figure 53. Single Frequency Sinusoidal Jitter Limits
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
84
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
