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MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
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Serial RapidIO  
components are included in this requirement. The reference impedance for return loss measurements is  
100-Ω resistive for differential return loss and 25-Ω resistive for common mode.  
Table 62. Receiver AC Timing Specifications—1.25 GBaud  
Range  
Characteristic  
Symbol  
Unit  
Notes  
Min  
Max  
Differential input voltage  
V
J
200  
0.37  
0.55  
1600  
mVp-p Measured at receiver  
UI p-p Measured at receiver  
UI p-p Measured at receiver  
IN  
Deterministic jitter tolerance  
D
Combined deterministic and random  
jitter tolerance  
J
DR  
1
Total jitter tolerance  
J
0.65  
UI p-p Measured at receiver  
T
Multiple input skew  
S
24  
ns  
Skew at the receiver input between lanes  
MI  
of a multilane link  
–12  
Bit error rate  
Unit interval  
Note:  
BER  
UI  
10  
ps  
800  
800  
±100 ppm  
1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The  
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component  
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.  
Table 63. Receiver AC Timing Specifications—2.5 GBaud  
Range  
Characteristic  
Symbol  
Unit  
Notes  
Min  
Max  
Differential input voltage  
V
J
200  
0.37  
0.55  
1600  
mVp-p Measured at receiver  
UI p-p Measured at receiver  
UI p-p Measured at receiver  
IN  
Deterministic jitter tolerance  
D
Combined deterministic and random  
jitter tolerance  
J
DR  
1
Total jitter tolerance  
J
0.65  
UI p-p Measured at receiver  
T
Multiple input skew  
S
24  
ns  
Skew at the receiver input between lanes  
MI  
of a multilane link  
–12  
Bit error rate  
Unit interval  
Note:  
BER  
UI  
10  
400  
400  
ps  
±100 ppm  
1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The  
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component  
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
Freescale Semiconductor  
83  
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