Serial RapidIO
17.8
Receiver Eye Diagrams
For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the
corresponding bit error rate specification (Table
when the eye pattern of the
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver
input compliance mask shown in
with the parameters specified in
The eye pattern of
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-Ω ± 5% differential resistive load.
V
DIFF
max
Receiver Differential Input Voltage
V
DIFF
min
0
–V
DIFF
min
–V
DIFF
max
0
A
B
Time (UI)
1-B
1-A
1
Figure 54. Receiver Input Compliance Mask
Table 65. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type
1.25 GBaud
2.5 GBaud
3.125 GBaud
V
DIFF
min
(mV)
100
100
100
V
DIFF
max
(mV)
800
800
800
A (UI)
0.275
0.275
0.275
B (UI)
0.400
0.400
0.400
17.9
Measurement and Test Requirements
Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in
Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly
guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
85
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
