Serial RapidIO
17.8 Receiver Eye Diagrams
For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the
corresponding bit error rate specification (Table 62, Table 63, Table 64) when the eye pattern of the
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver
input compliance mask shown in Figure 54 with the parameters specified in Table 65. The eye pattern of
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-Ω ± 5% differential resistive load.
V
max
DIFF
V
min
DIFF
DIFF
0
–V
min
–V
max
DIFF
0
1
A
B
1-B
1-A
Time (UI)
Figure 54. Receiver Input Compliance Mask
Table 65. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
V
min
(mV)
V
max
DIFF
(mV)
DIFF
Receiver Type
A (UI)
B (UI)
1.25 GBaud
2.5 GBaud
100
100
100
800
800
800
0.275
0.275
0.275
0.400
0.400
0.400
3.125 GBaud
17.9 Measurement and Test Requirements
Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in
Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly
guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
85
FREESCALE [ Freescale ]
