Serial RapidIO
17.5
Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long- and short-run interfaces at three
baud rates (a total of six cases) are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
in Clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to Serial RapidIO, as described in Section 8.1. The goal of this
standard is that electrical designs for Serial RapidIO can reuse electrical designs for XAUI, suitably
modified for applications at the baud intervals and reaches described herein.
17.6
Transmitter Specifications
LP-serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case shall be better than:
• –10 dB for (baud frequency)/10 < Freq(f) < 625 MHz, and
• –10 dB + 10log(f/625 MHz) dB for 625 MHz
≤
Freq(f)
≤
baud frequency
The reference impedance for the differential return loss measurements is 100-Ω resistive. Differential
return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components
related to the driver. The output impedance requirement applies to all valid output levels.
It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output,
in each case have a minimum value 60 ps.
It is recommended that the timing skew at the output of an LP-serial transmitter between the two signals
that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.
Table 55. Short Run Transmitter AC Timing Specifications—1.25 GBaud
Range
Characteristic
Symbol
Min
Output voltage
Differential output voltage
Deterministic jitter
Total jitter
Multiple output skew
Unit Interval
V
O
V
DIFFPP
J
D
J
T
S
MO
UI
–0.40
500
—
—
—
800
Max
2.30
1000
0.17
0.35
1000
800
V
mV p-p
UI p-p
UI p-p
ps
ps
Voltage relative to COMMON of either signal
comprising a differential pair
—
—
—
Skew at the transmitter output between lanes of a
multilane link
±100 ppm
Unit
Notes
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
79
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
